# 1 "dts/usrp_n300_fpga_XG.dts"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "dts/usrp_n300_fpga_XG.dts"






/dts-v1/;
/plugin/;

/{

# 1 "dts/n300-fpga.dtsi" 1






fragment@0 {
 target = <&fpga_region0>;
 reg = <0x0000>;
 #address-cells = <1>;
 #size-cells = <1>;
 __overlay__ {
  #address-cells = <1>;
  #size-cells = <1>;
  firmware-name = "n300.bin";
 };
};
# 13 "dts/usrp_n300_fpga_XG.dts" 2

fragment@1 {
 target = <&amba>;
 reg = <0x0001>;
 __overlay__ {
  nixge0: ethernet@40000000 {
   compatible = "ni,xge-enet-2.00";
   reg = <0x40000000 0x6000>;

   clocks = <&clkc 15>;
   clock-names = "bus_clk";

   nvmem-cells = <&eth1_addr>;
   nvmem-cell-names = "address";

   interrupts = <0 29 4>, <0 30 4>;
   interrupt-names = "rx", "tx";
   interrupt-parent = <&intc>;
   status = "okay";

   phy-mode = "xgmii";
   phy-handle = <&ethernet_phy1>;

   ethernet_phy1: ethernet-phy@4 {
    compatible = "ethernet-phy-ieee802.3-c45";
    reg = <4>;
   };
  };

  uio@40006000 {
   compatible = "usrp-uio";
   reg = <0x40006000 0x2000>;
   reg-names = "misc-enet-regs0";
   status = "okay";
  };

  nixge1: ethernet@40008000 {
   compatible = "ni,xge-enet-2.00";
   reg = <0x40008000 0x6000>;

   clocks = <&clkc 15>;
   clock-names = "bus_clk";

   nvmem-cells = <&eth2_addr>;
   nvmem-cell-names = "address";

   interrupts = <0 31 4>, <0 32 4>;
   interrupt-names = "rx", "tx";
   interrupt-parent = <&intc>;
   status = "okay";

   phy-mode = "xgmii";
   phy-handle = <&ethernet_phy2>;

   ethernet_phy2: ethernet-phy@4 {
    compatible = "ethernet-phy-ieee802.3-c45";
    reg = <4>;
   };
  };

  uio@4000e000 {
   compatible = "usrp-uio";
   reg = <0x4000e000 0x2000>;
   reg-names = "misc-enet-regs1";
   status = "okay";
  };
 };
};

# 1 "dts/n300-common.dtsi" 1






fragment@2 {
 target = <&amba>;
 reg = <0x0002>;
 __overlay__ {
  #address-cells = <1>;
  #size-cells = <1>;
  uio@40010000 {
   compatible = "usrp-uio";
   reg = <0x40010000 0x1000>;
   reg-names = "mboard-regs";
   status = "okay";
  };

  crossbar@40011000 {
   compatible = "ni,platform-crossbar-rp";
   reg = <0x40011000 0x1000>;
   status = "okay";
   rfnoc,ports = <0x10>;
   clocks = <&clkc 15>;
   clock-names = "bus_clk";
  };

  uio@40014000 {
   compatible = "usrp-uio";
   reg = <0x40014000 0x4000>;
   reg-names = "dboard-regs-0";
   status = "okay";
  };

  uio@42100000 {
   compatible = "usrp-uio";
   reg = <0x42100000 0x1000>;
   reg-names = "dboard-jtag-0";
   status = "okay";
  };
 };
};

fragment@5 {
 target = <&spi0>;
 reg = <0x0005>;
 __overlay__ {
  #address-cells = <1>;
  #size-cells = <0>;
  status = "okay";

  cs-gpios = <0>, <0>, <0>, <&gpio0 62 0>;

  spidev0: spidev@0 {
   compatible = "rohm,dh2228fv";
   reg = <0>;
   status = "okay";
   spi-max-frequency = <1000000>;
  };

  spidev1: spidev@1 {
   compatible = "rohm,dh2228fv";
   reg = <1>;
   status = "okay";
   spi-max-frequency = <1000000>;
  };

  spidev2: spidev@2 {
   compatible = "rohm,dh2228fv";
   reg = <2>;
   status = "okay";
   spi-max-frequency = <1000000>;
  };

  spidev3: spidev@3 {
   compatible = "rohm,dh2228fv";
   reg = <3>;
   status = "okay";
   spi-max-frequency = <1000000>;
  };
 };
};
# 83 "dts/usrp_n300_fpga_XG.dts" 2
# 1 "dts/dma-common.dtsi" 1






fragment@3 {
 target = <&amba>;
 reg = <0x0003>;
 __overlay__ {
  tx_dma0: dma@43CA0000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43CA0000 0x10000>;
   interrupts = <0 53 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <0>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <1>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  tx_dma1: dma@43CB0000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43CB0000 0x10000>;
   interrupts = <0 53 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <0>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <1>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  tx_dma2: dma@43CC0000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43CC0000 0x10000>;
   interrupts = <0 53 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <0>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <1>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  tx_dma3: dma@43CD0000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43CD0000 0x10000>;
   interrupts = <0 53 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <0>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <1>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  tx_dma4: dma@43CE0000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43CE0000 0x10000>;
   interrupts = <0 53 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <0>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <1>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  tx_dma5: dma@43CF0000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43CF0000 0x10000>;
   interrupts = <0 53 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <0>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <1>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  tx_dma6: dma@43D00000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43D00000 0x10000>;
   interrupts = <0 53 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <0>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <1>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  tx_dma7: dma@43D10000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43D10000 0x10000>;
   interrupts = <0 53 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <0>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <1>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  tx_dma8: dma@43D20000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43D20000 0x10000>;
   interrupts = <0 53 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <0>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <1>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  tx_dma9: dma@43D30000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43D30000 0x10000>;
   interrupts = <0 53 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <0>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <1>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  rx_dma0: dma@43C00000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43C00000 0x10000>;
   interrupts = <0 52 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <1>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <0>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  rx_dma1: dma@43C10000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43C10000 0x10000>;
   interrupts = <0 52 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <1>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <0>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  rx_dma2: dma@43C20000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43C20000 0x10000>;
   interrupts = <0 52 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <1>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <0>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  rx_dma3: dma@43C30000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43C30000 0x10000>;
   interrupts = <0 52 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <1>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <0>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  rx_dma4: dma@43C40000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43C40000 0x10000>;
   interrupts = <0 52 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <1>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <0>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  rx_dma5: dma@43C50000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43C50000 0x10000>;
   interrupts = <0 52 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <1>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <0>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  rx_dma6: dma@43C60000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43C60000 0x10000>;
   interrupts = <0 52 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <1>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <0>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  rx_dma7: dma@43C70000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43C70000 0x10000>;
   interrupts = <0 52 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <1>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <0>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  rx_dma8: dma@43C80000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43C80000 0x10000>;
   interrupts = <0 52 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <1>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <0>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };
  rx_dma9: dma@43C90000 {
   compatible = "adi,axi-dmac-1.00.a";
   reg = <0x43C90000 0x10000>;
   interrupts = <0 52 4>;
   clocks = <&clkc 15>;
   #dma-cells = <1>;
   adi,channels {
    #size-cells = <0>;
    #address-cells = <1>;
    dma-channel@0 {
     reg = <0>;
     adi,source-bus-type = <1>;
     adi,source-bus-width = <0x20>;
     adi,destination-bus-type = <0>;
     adi,destination-bus-width = <0x20>;
     adi,length-width = <24>;
    };
   };
  };


  usrp_rx_dma0: usrp-rx-dma@43c00000 {
   compatible = "ettus,usrp-rx-dma";
   dmas = <&rx_dma0 0>;
   dma-names = "dma";
   port-id = <0>;
   status = "okay";

   regmap = <&dma_conf0>;
   offset = <0x0>;
  };

  usrp_rx_dma1: usrp-rx-dma@43c10000 {
   compatible = "ettus,usrp-rx-dma";
   dmas = <&rx_dma1 0>;
   dma-names = "dma";
   port-id = <1>;

   regmap = <&dma_conf0>;
   offset = <0x4>;
  };

  usrp_rx_dma2: usrp-rx-dma@43c20000 {
   compatible = "ettus,usrp-rx-dma";
   dmas = <&rx_dma2 0>;
   dma-names = "dma";
   port-id = <2>;

   regmap = <&dma_conf0>;
   offset = <0x8>;
  };

  usrp_rx_dma3: usrp-rx-dma@43c30000 {
   compatible = "ettus,usrp-rx-dma";
   dmas = <&rx_dma3 0>;
   dma-names = "dma";
   port-id = <3>;

   regmap = <&dma_conf0>;
   offset = <0xc>;
  };

  usrp_rx_dma4: usrp-rx-dma@43c40000 {
   compatible = "ettus,usrp-rx-dma";
   dmas = <&rx_dma4 0>;
   dma-names = "dma";
   port-id = <4>;

   regmap = <&dma_conf0>;
   offset = <0x10>;
  };

  usrp_rx_dma5: usrp-rx-dma@43c50000 {
   compatible = "ettus,usrp-rx-dma";
   dmas = <&rx_dma5 0>;
   dma-names = "dma";
   port-id = <5>;

   regmap = <&dma_conf0>;
   offset = <0x14>;
  };

  usrp_rx_dma6: usrp-rx-dma@43c60000 {
   compatible = "ettus,usrp-rx-dma";
   dmas = <&rx_dma6 0>;
   dma-names = "dma";
   port-id = <6>;

   regmap = <&dma_conf0>;
   offset = <0x18>;
  };

  usrp_rx_dma7: usrp-rx-dma@43c70000 {
   compatible = "ettus,usrp-rx-dma";
   dmas = <&rx_dma7 0>;
   dma-names = "dma";
   port-id = <7>;

   regmap = <&dma_conf0>;
   offset = <0x1c>;
  };

  usrp_rx_dma8: usrp-rx-dma@43c80000 {
   compatible = "ettus,usrp-rx-dma";
   dmas = <&rx_dma8 0>;
   dma-names = "dma";
   port-id = <8>;

   regmap = <&dma_conf0>;
   offset = <0x20>;
  };

  usrp_rx_dma9: usrp-rx-dma@43c90000 {
   compatible = "ettus,usrp-rx-dma";
   dmas = <&rx_dma9 0>;
   dma-names = "dma";
   port-id = <9>;

   regmap = <&dma_conf0>;
   offset = <0x24>;
  };

  usrp_tx_dma0: usrp-tx-dma@43ca0000 {
   compatible = "ettus,usrp-tx-dma";
   dmas = <&tx_dma0 0>;
   dma-names = "dma";
   port-id = <0>;
  };

  usrp_tx_dma1: usrp-tx-dma@43cb0000 {
   compatible = "ettus,usrp-tx-dma";
   dmas = <&tx_dma1 0>;
   dma-names = "dma";
   port-id = <1>;
  };

  usrp_tx_dma2: usrp-tx-dma@43cc0000 {
   compatible = "ettus,usrp-tx-dma";
   dmas = <&tx_dma2 0>;
   dma-names = "dma";
   port-id = <2>;
   status = "okay";
  };

  usrp_tx_dma3: usrp-tx-dma@43cd0000 {
   compatible = "ettus,usrp-tx-dma";
   dmas = <&tx_dma3 0>;
   dma-names = "dma";
   port-id = <3>;
  };

  usrp_tx_dma4: usrp-tx-dma@43ce0000 {
   compatible = "ettus,usrp-tx-dma";
   dmas = <&tx_dma4 0>;
   dma-names = "dma";
   port-id = <4>;
   status = "okay";
  };

  usrp_tx_dma5: usrp-tx-dma@43cf0000 {
   compatible = "ettus,usrp-tx-dma";
   dmas = <&tx_dma5 0>;
   dma-names = "dma";
   port-id = <5>;
  };

  usrp_tx_dma6: usrp-tx-dma@43d00000 {
   compatible = "ettus,usrp-tx-dma";
   dmas = <&tx_dma6 0>;
   dma-names = "dma";
   port-id = <6>;
  };

  usrp_tx_dma7: usrp-tx-dma@43d10000 {
   compatible = "ettus,usrp-tx-dma";
   dmas = <&tx_dma7 0>;
   dma-names = "dma";
   port-id = <7>;
  };

  usrp_tx_dma8: usrp-tx-dma@43d20000 {
   compatible = "ettus,usrp-tx-dma";
   dmas = <&tx_dma8 0>;
   dma-names = "dma";
   port-id = <8>;
  };

  usrp_tx_dma9: usrp-tx-dma@43d30000 {
   compatible = "ettus,usrp-tx-dma";
   dmas = <&tx_dma9 0>;
   dma-names = "dma";
   port-id = <9>;
  };

  ps_dma_dest_regs@42000000 {
   compatible = "usrp-uio";
   reg = <0x42000000 0x1000>;
   reg-names = "liberio";
   status = "okay";
  };

  dma_conf0: dma_conf0@42080000 {
   compatible = "syscon";
   reg = <0x42080000 0x1000>;
   status = "okay";
  };
 };
};
# 84 "dts/usrp_n300_fpga_XG.dts" 2

};
