# 1 "dts/usrp_n310_fpga_WX.dts"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "dts/usrp_n310_fpga_WX.dts"





/dts-v1/;
/plugin/;

# 1 "dts/n310-fpga.dtsi" 1





&fpga_full {
 firmware-name = "n310.bin";
};
# 10 "dts/usrp_n310_fpga_WX.dts" 2

&fpga_full {
 uio@40006000 {
  compatible = "usrp-uio";
  reg = <0x40006000 0x2000>;
  reg-names = "misc-enet-regs0";
  status = "okay";
 };

 nixge1: ethernet@40008000 {
  compatible = "ni,xge-enet-2.00";
  reg = <0x40008000 0x6000>;

  clocks = <&clkc 15>;
  clock-names = "bus_clk";

  nvmem-cells = <&eth2_addr>;
  nvmem-cell-names = "address";

  interrupts = <0 31 4>, <0 32 4>;
  interrupt-names = "rx", "tx";
  interrupt-parent = <&intc>;
  status = "okay";

  phy-mode = "xgmii";
  phy-handle = <&ethernet_phy2>;

  mdio {
   ethernet_phy2: ethernet-phy@4 {
    compatible = "ethernet-phy-ieee802.3-c45";
    reg = <4>;
   };
  };
 };

 uio@4000e000 {
  compatible = "usrp-uio";
  reg = <0x4000e000 0x2000>;
  reg-names = "misc-enet-regs1";
  status = "okay";
 };

 uio@43d40000 {
  compatible = "usrp-uio";
  reg = <0x43d40000 0x40000>;
  reg-names = "wr-regs";
  status = "okay";
 };

 uart2@42c00000 {
  compatible = "xlnx,xps-uartlite-1.00.a";
  reg = <0x42c00000 0x1000>;
  interrupt-parent = <&intc>;
  interrupts = <0 54 4>;
 };
};

# 1 "dts/n310-common.dtsi" 1





&fpga_full {
 uio@40010000 {
  compatible = "usrp-uio";
  reg = <0x40010000 0x2000>;
  reg-names = "mboard-regs";
  status = "okay";
 };

 uio@40014000 {
  compatible = "usrp-uio";
  reg = <0x40014000 0x4000>;
  reg-names = "dboard-regs-0";
  status = "okay";
 };

 uio@40018000 {
  compatible = "usrp-uio";
  reg = <0x40018000 0x4000>;
  reg-names = "dboard-regs-1";
  status = "okay";
 };

 uio@42100000 {
  compatible = "usrp-uio";
  reg = <0x42100000 0x1000>;
  reg-names = "dboard-jtag-0";
  status = "okay";
 };

 uio@42200000 {
  compatible = "usrp-uio";
  reg = <0x42200000 0x1000>;
  reg-names = "dboard-jtag-1";
  status = "okay";
 };

};

&spi0 {
 status = "okay";

 cs-gpios = <0>, <0>, <0>, <&gpio0 62 0>;

 spidev0: spidev@0 {
  compatible = "rohm,dh2228fv";
  reg = <0>;
  status = "okay";
  spi-max-frequency = <1000000>;
 };

 spidev1: spidev@1 {
  compatible = "rohm,dh2228fv";
  reg = <1>;
  status = "okay";
  spi-max-frequency = <1000000>;
 };

 spidev2: spidev@2 {
  compatible = "rohm,dh2228fv";
  reg = <2>;
  status = "okay";
  spi-max-frequency = <1000000>;
 };

 spidev3: spidev@3 {
  compatible = "rohm,dh2228fv";
  reg = <3>;
  status = "okay";
  spi-max-frequency = <1000000>;
 };
};

&spi1 {
 status = "okay";

 cs-gpios = <0>, <0>, <0>, <&gpio0 63 0>;

 spidev4: spidev@0 {
  compatible = "rohm,dh2228fv";
  reg = <0>;
  status = "okay";
  spi-max-frequency = <1000000>;
 };

 spidev5: spidev@1 {
  compatible = "rohm,dh2228fv";
  reg = <1>;
  status = "okay";
  spi-max-frequency = <1000000>;
 };

 spidev6: spidev@2 {
  compatible = "rohm,dh2228fv";
  reg = <2>;
  status = "okay";
  spi-max-frequency = <1000000>;
 };

 spidev7: spidev@3 {
  compatible = "rohm,dh2228fv";
  reg = <3>;
  status = "okay";
  spi-max-frequency = <1000000>;
 };
};
# 68 "dts/usrp_n310_fpga_WX.dts" 2
# 1 "dts/dma-common.dtsi" 1





&fpga_full {
 nixge_internal: ethernet@40040000 {
  #address-cells = <1>;
  #size-cells = <1>;
  compatible = "ni,xge-enet-3.00";
  reg = <0x40040000 0x4000
         0x40050000 0x2000>;
  reg-names = "dma", "ctrl";
   clocks = <&clkc 15>;
   clock-names = "bus_clk";

  interrupts = <0 52 4>, <0 53 4>;
  interrupt-names = "rx", "tx";
  interrupt-parent = <&intc>;
  status = "okay";

  phy-mode = "internal";
  local-mac-address = <0x00 0x01 0x02 0x03 0x04 0x05>;

  fixed-link {
   speed = <1000>;
   full-duplex;
  };
 };

 uio@40052000 {
  compatible = "usrp-uio";
  reg = <0x40052000 0x2000>;
  reg-names = "misc-enet-int-regs";
  status = "okay";
 };
};
# 68 "dts/usrp_n310_fpga_WX.dts" 2
