<?xml version="1.0">
<nidocument>
<nicomment>
<nifamily displayname="USRP RIO" familyname="USRP RIO">
</nifamily>
</nicomment>
<nierror code="-1074100545">
Invalid parameter. The offset to start reading from or writing to is out-of-range or too high for the subsystem.
</nierror>
<nierror code="-1074100546">
Invalid parameter. The amount of data to read or write is out-of-range or too large for this subsystem.
</nierror>
<nierror code="-1074100547">
The offset plus the amount of data to read or write is out-of-range or too large for this subsystem.
</nierror>
<nierror code="-1074100548">
Invalid parameter. The handle parameter was NULL.
</nierror>
<nierror code="-1074100549">
Invalid parameter. The deviceIdentifiers parameter was NULL.
</nierror>
<nierror code="-1074100550">
Invalid parameter. The serialNumbers parameter was NULL.
</nierror>
<nierror code="-1074100551">
Invalid parameter. The data parameter was NULL.
</nierror>
<nierror code="-1074100552">
The size of the supplied bitstream is too large.
</nierror>
<nierror code="-1074100553">
Invalid parameter. The buffer parameter was NULL.
</nierror>
<nierror code="-1074100554">
The size of the supplied buffer is too small.
</nierror>
<nierror code="-1074100555">
The FPGA device support object is NULL and likely has not yet been created. There is likely an error between the FPGA driver and the board driver.
</nierror>
<nierror code="-1074100556">
Invalid parameter. The value of the subsystem parameter did not correspond to a valid subsystem.
</nierror>
<nierror code="-1074100557">
Configuring the FPGA auto load mode is not supported. The FPGA will always automatically load on a reset or a power event.
</nierror>
<nierror code="-1074100558">
Invalid parameter. The value of the property parameter did not correspond to a valid property.
</nierror>
<nierror code="-1074100563">
The FPGA was programmed with a Data Clock rate different from what the FPGA was compiled for. The correct/matching rate must be specified via the 'Data Clock rate' control on the Open VI.
</nierror>
<nierror code="-1074100564">
The Time library signature on the host does not match the FPGA. Recompile the FPGA.
</nierror>
<nierror code="-1074100565">
Failed to set future event.

Details:
A valid future event has already been set. Force a new future event to override the current future event.
</nierror>
<nierror code="-1074100566">
Failed to set future event.

Details:
The future event time was in the past. A valid future event time must be in the future.
</nierror>
<nierror code="-1074100567">
Reading the FPGA time from the next CPTR is not valid. Read the FPGA time now or from the previous CPTR.
</nierror>
<nierror code="-1074100568">
Writing the FPGA time at the previous CPTR is not valid. Write the FPGA time now or at the next CPTR.
</nierror>
<nierror code="-1074100569">
Setting the time on multiple devices is only valid when setting at the next CPTR.
</nierror>
<nierror code="-1074100570">
Failed to set the time on all the devices.

Details:
Setting the time on all the devices may not have completed within one CPTR period. The time may not be correct on all the devices.
</nierror>
<nierror code="-1074100571">
Failed to set the time on all the devices.

Details:
Did not set the time on all the devices to the correct time.
</nierror>
<nierror code="-1074100572">
Failed to set the time on all the devices.

Details:
Timed out while waiting for CPTR. This may be due to misconfiguring CPTR on the FPGA or setting timeout less than the CPTR period.
</nierror>
<nierror code="-1074100573">
The Time library on the host is not compatible with the FPGA. The FPGA is too new for the host. Upgrade the software.
</nierror>
<nierror code="-1074100574">
The Time library on the host is not compatible with the FPGA. The host is too new for the FPGA. Recompile the FPGA.
</nierror>
<nierror code="-1074100575">
The Synchronization library signature on the host does not match the FPGA. Recompile the FPGA.
</nierror>
<nierror code="-1074100576">
The Synchronization library on the host is not compatible with the FPGA. The FPGA is too new for the host. Upgrade the software.
</nierror>
<nierror code="-1074100577">
The Synchronization library on the host is not compatible with the FPGA. The host is too new for the FPGA. Recompile the FPGA.
</nierror>
<nierror code="-1074100578">
Synchronization failed due to lack of confidence.

Details:
The devices may be synchronized even if the required confidence was not met. Synchronization may have failed due to improper system configuration. Refer to the NI-USRP Help for information about how to configure the system for synchronization. For example, if the confidence level reported is approximately 1/CPTR period percent, the device clocks likely do not have a fixed phase relationship or are not locked to a common reference clock.
</nierror>
<nierror code="-1074100579">
An invalid CPTR adjust value was produced.
</nierror>
<nierror code="-1074100580">
Synchronization failed. The measurement circuit failed to become ready.
</nierror>
<nierror code="-1074100581">
Synchronization failed because the devices did not align with their CPTRs.

Details:
Synchronization may have failed due to improper system configuration. Refer to the NI-USRP Help for information about to configure the system for synchronization.

To continue, confirm proper system configuration. Then perform one of the following:
- Retry.
- Change the phase relationship of the device clocks.

Cabling and system configuration affects the phase relationship of the device clocks. Use length-matched cables to reduce static clock phase skew.
</nierror>
<nierror code="-1074100582">
A CPTR Period must be provided for every device participating in synchronization.
</nierror>
<nierror code="-1074100583">
Synchronization failed. The measurement circuit has exceeded the maximum number of attempts to perform a measurement. This can occur only if the measurement circuit is not properly wired or connected on the FPGA block diagram or if the measurement circuit is malfunctioning.
</nierror>
<nierror code="-1074100584">
The device does not contain valid characterization data, which is required to configure reference level, output power, or correct I/Q impairments.
</nierror>
<nierror code="-1074100585">
Specified reference level or output power exceeds the characterized capabilities of the device.
</nierror>
<nierror code="-1074100586">
Specified values exceed the characterized capabilities.
</nierror>
<nierror code="-1074100587">
Invalid reference frequency source. Valid sources are REF IN, Internal, and GPS.
</nierror>
<nierror code="-1074100588">
Timeout waiting for operation to complete.
</nierror>
<nierror code="-1074100589">
Hardware is too old for this version of the Configuration Instrument Design Library.
</nierror>
<nierror code="-1074100590">
Hardware is too new for this version of the Configuration Instrument Design Library.
</nierror>
<nierror code="-1074100591">
Hardware EEPROM Map and/or calibration data is too old for this version of the Configuration Instrument Design Library.
</nierror>
<nierror code="-1074100592">
Hardware EEPROM Map and/or calibration data is too new for this version of the Configuration Instrument Design Library.
</nierror>
<nierror code="-1074100593">
Unsupported or unknown daughterboard ID.
</nierror>
<nierror code="-1074100594">
The Configuration library signature on the host does not match the FPGA. Recompile FPGA.
</nierror>
<nierror code="-1074100595">
The Configuration library on the host is not compatible with the FPGA. The FPGA is too new for the host. Upgrade the software.
</nierror>
<nierror code="-1074100596">
The Configuration library on the host is not compatible with the FPGA. The host is too new for the FPGA. Recompile the FPGA.
</nierror>
<nierror code="-1074100597">
The fixed logic on the FPGA is not compatible with the host. The FPGA is too new for the host. Upgrade the software.
</nierror>
<nierror code="-1074100598">
The fixed logic on the FPGA is not compatible with the host. The host is too new for the FPGA. Upgrade the fixed logic and recompile the FPGA.
</nierror>
<nierror code="-1074100599">
Invalid number of bits for SPI command.
</nierror>
<nierror code="-1074100600">
Invalid LMK04816 SPI instruction.
</nierror>
<nierror code="-1074100601">
Invalid scope or channel specifier.
</nierror>
<nierror code="-1074100602">
Unsupported data section.
</nierror>
<nierror code="-1074100603">
The Configuration library on the host is not compatible with the FPGA. The FPGA is too new for the host. Upgrade the software.
</nierror>
<nierror code="-1074100604">
The Configuration library on the host is not compatible with the FPGA. The host is too new for the FPGA. Recompile the FPGA.
</nierror>
<nierror code="-1074100605">
The specified device is unknown. Enter or select a valid device.
</nierror>
<nierror code="-1074100606">
Checksum did not match. GPS NMEA data is corrupt. There may be a problem with the device. Contact National Instruments if this problem persists.
</nierror>
<nierror code="-1074100607">
Device enumeration error. Either no devices were found, or more than one device was found with the resource name you entered. Verify that the resource name matches the device name in MAX.
</nierror>
<nierror code="-1074100608">
An unknown antenna was specified. Enter a valid antenna name. Valid antenna names are RX1, RX2, TX1, and TX/RX.
</nierror>
<nierror code="1073383040">
You need to make a one-time update to the Rx reference level correction data on the device. You can update the correction data by running <vi.lib>\LabVIEW Targets\FPGA\USRP\niusrprio_tools.llb\Update Device Correction Data.vi. For more information, go to http://www.ni.com/kb and search for 6P9BI1M5.
</nierror>
<nierror code="1073383041">
GPS NMEA data is not yet initialized. To prevent this warning, wait for a few seconds before you query data the first time after you open a session.
</nierror>
<nierror code="1073383042">
Daughterboard configuration mismatch. The operating bandwidth of the daughterboards does not match how the daughterboards were configured.
</nierror>
<nierror code="1073383043">
You are using a bitfile configured for a data clock that is slower than the rate required for the bandwidth of this device. This may result in aliasing in your signal.
</nierror>
<nierror code="1073383044">
An older version of the Synchronization library has been detected on the FPGA. This older library may falsely report successful synchronization. Recompile the FPGA to fix this issue, or re-download the FPGA bitfile each run as a work-around.
</nierror>
</nidocument>
